I misunderstood how the I2S FIFO works and thus had miscalculated the delay from writing the FIFO until the data appears on the output. That resulted in sporadic TMC driver initialization failures.
[FluidNC PR#1475] Fix I2S delay – fixes #1446
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![[gnea/grbl-Mega Issue#1] $ command extentions](https://www.grblhal.com/wp-content/themes/gitphp/timthumb.php?src=https://www.grblhal.com/wp-content/themes/gitphp/assets/img/pic/2.jpg&h=110&w=185&q=90&zc=1&ct=1)
[gnea/grbl-Mega Issue#1] $ command extentions -
![[gnea/grbl-Mega Issue#2] Better interrupt priorities](https://www.grblhal.com/wp-content/themes/gitphp/timthumb.php?src=https://www.grblhal.com/wp-content/themes/gitphp/assets/img/pic/12.jpg&h=110&w=185&q=90&zc=1&ct=1)
[gnea/grbl-Mega Issue#2] Better interrupt priorities -
![[gnea/grbl-Mega Issue#3] ATMega16U2 virtual com port on ATMega2560](https://www.grblhal.com/wp-content/themes/gitphp/timthumb.php?src=https://www.grblhal.com/wp-content/themes/gitphp/assets/img/pic/6.jpg&h=110&w=185&q=90&zc=1&ct=1)
[gnea/grbl-Mega Issue#3] ATMega16U2 virtual com port on ATMega2560 -
![[gnea/grbl-Mega Issue#4] Real-time adjustable feedrates](https://www.grblhal.com/wp-content/themes/gitphp/timthumb.php?src=https://www.grblhal.com/wp-content/themes/gitphp/assets/img/pic/2.jpg&h=110&w=185&q=90&zc=1&ct=1)
[gnea/grbl-Mega Issue#4] Real-time adjustable feedrates
- [gnea/grbl-Mega Issue#1] $ command extentions
- [gnea/grbl-Mega Issue#2] Better interrupt priorities
- [gnea/grbl-Mega Issue#3] ATMega16U2 virtual com port on ATMega2560
- [gnea/grbl-Mega Issue#4] Real-time adjustable feedrates
- [gnea/grbl-Mega Issue#5] question about the download zip contents
- [gnea/grbl-Mega Issue#6] Adding outputs for external state signals
- [gnea/grbl-Mega Issue#7] which g-code sender is being used in grbl-Mega testing?
- [gnea/grbl-Mega Issue#8] Frecuencia y velocidad de avance.